STT-MRAM Based NoC Buffer Design

As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leakage power, and displays higher memory density compared to conventional SRAM. But STT-MRAM suffers from inherit drawbacks like multi cycle write latency and high write power consumption. So, these problem have to addressed in order to have an efficient design to incorporate STT-MRAM for NoC input buffer instead of traditional SRAM based input buffer design. Motivated by short intra-router latency, previously proposed write latency reduction technique is explored by sacrificing retention time and a hybrid design of input buffers using both SRAM and STT-MRAM to "hide" the long write latency efficiently is proposed. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer is also proposed

Proceedings of National Conference on Relevance of Engineering and Science for Environment and Society

This conference proceedings contains articles on the various research ideas of the academic community and practitioners presented at the National Conference on Relevance of Engineering and Science for Environment and Society (R{ES}2 2021). R{ES}2 2021 was organized by Shri Pandurang Pratishthan’s, Karmayogi Engineering College, Shelve, Pandharpur, India on July 25th, 2021. Conference Title: National Conference on Relevance of Engineering and Science for Environment and SocietyConference Acronym: R{ES}2 2021Conference Date: 25 July 2021Conference Location: Online (Virtual Mode)Conference Organizers: Shri Pandurang Pratishthan’s, Karmayogi Engineering College, Shelve, Pandharpur, India